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68 lines
2.3 KiB
C
68 lines
2.3 KiB
C
#ifndef ULTRA64_RCP_H
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#define ULTRA64_RCP_H
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struct HardwareRegisters
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{
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uintptr_t SP_MEM_ADDR_REG = 0; // = 0x04040000;
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uintptr_t SP_DRAM_ADDR_REG = 0; // = 0x04040004;
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uintptr_t SP_RD_LEN_REG = 0; // = 0x04040008;
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uintptr_t SP_WR_LEN_REG = 0; // = 0x0404000C;
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uintptr_t SP_STATUS_REG = 0; // = 0x04040010;
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uintptr_t SP_PC_REG = 0; // = 0x04080000;
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uintptr_t MI_INIT_MODE_REG = 0; // = 0x04300000;
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uintptr_t MI_VERSION_REG = 0; // = 0x04300004;
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uintptr_t MI_INTR_REG = 0; // = 0x04300008;
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uintptr_t MI_INTR_MASK_REG = 0; // = 0x0430000C;
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uintptr_t VI_STATUS_REG = 0; // = 0x04400000;
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uintptr_t VI_ORIGIN_REG = 0; // = 0x04400004;
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uintptr_t VI_WIDTH_REG = 0; // = 0x04400008;
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uintptr_t VI_INTR_REG = 0; // = 0x0440000C;
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uintptr_t VI_CURRENT_REG = 0; // = 0x04400010;
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uintptr_t VI_BURST_REG = 0; // = 0x04400014;
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uintptr_t VI_V_SYNC_REG = 0; // = 0x04400018; // VI vertical sync
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uintptr_t VI_H_SYNC_REG = 0; // = 0x0440001C; // VI horizontal sync
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uintptr_t VI_LEAP_REG = 0; // = 0x04400020; // VI horizontal sync leap
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uintptr_t VI_H_START_REG = 0; // = 0x04400024; // VI horizontal video
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uintptr_t VI_V_START_REG = 0; // = 0x04400028; // VI vertical video
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uintptr_t VI_V_BURST_REG = 0; // = 0x0440002C; // VI vertical burst
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uintptr_t VI_X_SCALE_REG = 0; // = 0x04400030; // VI x-scale
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uintptr_t VI_Y_SCALE_REG = 0; // = 0x04400034; // VI y-scale
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uintptr_t AI_DRAM_ADDR_REG = 0; // = 0x04500000;
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uintptr_t AI_LEN_REG = 0; // = 0x04500004;
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uintptr_t AI_CONTROL_REG = 0; // = 0x04500008;
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intptr_t AI_STATUS_REG = 0; // = 0x0450000C;
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uintptr_t AI_DACRATE_REG = 0; // = 0x04500010;
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uintptr_t AI_BITRATE_REG = 0; // = 0x04500014;
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};
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extern HardwareRegisters hw_regs;
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#define AI_STATUS_AI_FULL (1 << 31)
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#define AI_STATUS_AI_BUSY (1 << 30)
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#define PI_STATUS_BUSY 0x1
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#define PI_STATUS_IOBUSY 0x2
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#define PI_STATUS_ERROR 0x4
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#define PI_STATUS_RESET_CONTROLLER 0x1
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#define PI_STATUS_CLEAR_INTR 0x2
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#define SI_STATUS_DMA_BUSY 0x1
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#define SI_STATUS_IO_READ_BUSY 0x2
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#define SI_STATUS_DMA_ERROR 0x8
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#define SI_STATUS_INTERRUPT (1 << 12)
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#define PIF_RAM_START 0x1FC007C0
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#define VI_NTSC_CLOCK 48681812 /* Hz = 48.681812 MHz */
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#define VI_PAL_CLOCK 49656530 /* Hz = 49.656530 MHz */
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#define VI_MPAL_CLOCK 48628316 /* Hz = 48.628316 MHz */
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#endif
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